The present disclosure relates generally to semiconductor devices. More particularly, the present disclosure relates to scaling of semiconductor devices.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the electrical performance of the device. As the conductive elements of the structure are positioned closer and closer together, and the amount of dielectric material separating the conductive elements is decreased, the parasitic capacitance of the structure increases.